Hey Everyone 👋, Welcome back. We have covered Introduction to Verilog in detail in our previous article. In this blog post, we will discuss how semiconductor industries are manufacturing Integrated Chips also knows as IC Design Flow or VLSI Design Flow in very detailed.

Are you ready to learn? So, Let’s get started.

VLSI Design Flow

Very Large Scale Integration (VLSI) design flow is the process of designing an Integrated Chip by taking customer’s specifications. The steps involved in this design flow are System specifications, Architectural design, Functional design & Logic design, Circuit design, Physical verification & Tape-out, Wafer preparation, Final IC with the package. A detailed description of each step in the design flow is discussed below. A typical design cycle may be represented by the flow chart as shown in the figure.

System Specifications (Design Specifications):

The first step of any design process is to lay down the specifications of the system. System specification is a high-level representation of the system. The factors to be considered in this process include performance, functionality, and physical dimensions. The fabrication technology and design techniques are also considered. The specification of a system is a compromise between market requirements, technology, and economic viability. The end results are specifications for the size, speed, power, and functionality of VLSI system.

To clear this concept, let’s take an example of Ripple Carry Adder (4-bit wide), which means that it takes two inputs namely A, B each of four-bit wide adds them and gives resultant sum as output. In this example, system specifications are inputs A, B, and output sum, functionality as the name indicates it adds two numbers, how much delay it should take, how much power it should consume, with what frequency it should work, with what technology (45nm, 90nm, 180nm, etc.) it should fabricate and many more comes into picture. The design specifications of Ripple Carry Adder is shown below:

Note: Design Specifications are based on customer requirement.

Architectural Design:

The basic architecture of the system is designed in this step. This includes such decisions as RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer), number of ALUs, Floating point units, number, and structure of pipelines, and size of caches among others. The outcome of architectural design is a Micro-Architectural (MAS) Specifications. While MAS is a textual description, architects can accurately predicts the performance, power and die size of the design based on such a description.

To clear this concept, by considering Ripple Carry Adder (4-bit wide) as an example, inside the architecture of Ripple Carry Adder we have four Full Adder modules namely FA0, FA1, FA2, FA3, and their interconnections as shown in the figure below:

Functional Design (Behavioral):

As shown in figure – 3, In this step the main functional units of the system are identified. This also identifies the interconnect requirements between the units. The area, power, and other parameters of each unit are estimated. The key idea is to specify behavior, in terms of inputs, outputs, and timing of each unit, without specifying its internal structure.

The outcome of functional design is usually a timing diagram or other relationships
between units. This information leads to improvement of the overall design process and reduction of the complexity of subsequent phases. The functional or behavioral design provides quick emulation of the system and allows fast debugging of the full system. Behavioral design is largely a manual step with little or no automation help available.

Logic Design:

In this step, the control flow, word widths, register allocation, arithmetic operations, and logic operations of the design that represent the functional design are derived and tested. This description is called Register Transfer Level (RTL) description. RTL is expressed in a Hardware Description Language (HDL), such as VHDL or Verilog. This description can be used in simulation and verification. This description consists of boolean expressions and timing information. The Boolean expressions are minimized to achieve the smallest logic design which confirms to the functional design. This logic design of the system is simulated and tested to verify its correctness. In some special cases, logic design can be automated using high-level synthesis tools. These tools produce an RTL description from a behavioral description of the design.

To clear this concept, let’s see the logic design by taking an example Ripple Carry Adder (4-bit wide) using Verilog HDL as shown below:

//Code for FULLADDER
module FullAdder(cout,sum,a,b,cin);
input a,b,cin;
output cout,sum;

xor v2(sum,a,b,cin);
and b1(t1,a,b);
and b2(t2,cin,b);
and b3(t3,a,cin);
or j1(cout,t1,t2,t3);

endmodule

//Code for RippleCarryAdder
module Ripple_Carry_Adder(cout,S,A,B);
input [3:0]A,B;
output [3:0]S;
output cout;
wire [3:0]S;
wire c0,c1,c2;

FullAdder FA0 (c0,S[0],A[0],B[0],1'b0);
FullAdder FA1 (c1,S[1],A[1],B[1],c0);
FullAdder FA2 (c2,S[2],A[2],B[2],c1);
FullAdder FA3 (cout,S[3],A[3],B[3],c2);

endmodule

//Testbench for RippleCarryAdder 
//Note: This file is not included as design but this testbench code is used to verify 
        whether the RippleCarryAdder is properly working or not.
module tb;
reg [3:0]A,B;
wire [3:0]S;
wire cout;

Ripple_Carry_Adder inst(cout,S,A,B);
initial begin
repeat(10)
begin
A=$random;
B=$random;
#1;
$display(A,B,"::",{cout,S});
end
end
endmodule

Circuit Design:

The purpose of circuit design is to develop a circuit representation based on
the logic design. The Boolean expressions are converted into a circuit representation by taking into consideration the speed and power requirements of the original design. Circuit simulation is used to verify the correctness and timing of each component. The circuit design is usually expressed in a detailed circuit diagram. This diagram shows the circuit elements (cells, macros, gates, transistors) and interconnection between these elements. This representation is also called a netlist. Tools used to manually enter such description are called schematic capture tools. In many cases, a netlist can be created automatically from logic (RTL) description by using synthesis tools.

To clear this concept, let’s see the Circuit Design of our example Ripple Carry Adder (4-bit wide) as shown in the figure below:

Physical Design:

In this step, the circuit representation or net list is converted into a geometric representation. This geometric representation of a circuit is called a layout. The layout is created by converting each logic component like cells, macros, gates, transistors into a geometric representation of specific shapes in multiple layers, which perform the intended logic function of the corresponding component. Connections between different components are also expressed as geometric patterns typically line in multiple layers. The exact details of the layout also depend on design rules, which are guidelines based on the limitations of the fabrication process and the electrical properties of the fabrication materials. Physical design is a very complex process and therefore it is usually broken down into various sub-steps. Various verification and validation checks are performed on the layout during physical design. In many cases, physical design can he completely or partially automated and layout can be generated directly from net list by Layout Synthesis tools. Layout synthesis tools, while fast do have an area and performance penalty. Which limit their use to some designs. Manual layout, while slow and manually intensive, does have a better area and performance as compared to the synthesized layout. However, this advantage may dissipate as larger and larger designs may undermine human capability to comprehend and obtain globally optimized solutions.

The flow of physical design is shown in the below figure:

Below are some schematics of physical design for our example Ripple Carry Adder (4-bit wide) designed using Cadence tool:

Physical Verification:

After the layout, verification is done which includes the steps shown in the flow above. Then the design is ready for fabrication. Since layout data is typically sent to fabrication on tape, the event of the release of data is called Tape Out.

Wafer Sorting:

Wafer testing is a step performed during semiconductor device fabrication. Wafer Testing is performed before a wafer is sent to die preparation. All individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns.

Final Test:

Final Test eliminates devices having assembly defects.

Conclusion:

This is all about Integrated Chip (IC) Design Flow. In next blog we will directly jump into Advanced Digital Design Concepts with Verilog HDL. Until then, stay safe. Cheers✌.